1. Field of the Present Invention
The present invention relates to a semiconductor integrated circuit and more particularly to a synchronous delay circuit for generating a synchronously delayed signal with a short time and a frequency multiplying circuit using the same in a semiconductor device.
2. Description of the Related Art
As a conventional example of a synchronous delay circuit using a sequence of delay circuits, a circuit is proposed in, for example, "A Multimedia 32b RISC Microprocessor with 16 Mb DRAM" by T. Shimizu, (IEEE International Solid-State Circuit Conference 1996, ISSCC Digest of Technical Papers, Feb., 1996, pp. 216 to 217). FIG. 1 shows the synchronous delay circuit in the case where the frequency of a clock signal is multiplied by 4 times.
Referring to FIG. 1, four sequences of delay circuits, i.e., first to fourth sequences of delay circuits 401 to 404 are connected in serial. The output terminal of each of the first to fourth sequences of delay circuits 401 to 404 is selected by a corresponding one of four switches, i.e., first to fourth switches 405 to 408. A first clock signal 411 is supplied to the first sequence of delay circuits and a phase comparator 409. A fifth clock signal 415 which passed the first to fourth sequences of delay circuits 401 to 404 is also supplied to the phase comparator 409. The phase comparator 409 compares the first clock signal 411 and the fifth clock signal 415 and generates an UP signal 416 or a DOWN signal 417 based on the comparing result. The UP signal 416 or the DOWN signal 417 is supplied to a counter (UP/DOWN counter) 410.
The counter 410 generates a control signal 418 based on the UP signal 416 or DOWN signal 416, and supplies the control signal to the first to fourth switches 405 to 408. As a result, the phase of the fifth clock signal 415 is set to be equal to the phase of the first clock signal 411.
Delay times of the first to fourth sequence of delay circuits 401 to 404 are equally adjusted. As a result, a time difference between adjacent two of the first clock signal 411, a second clock signal 412, a third clock signal 413, and a fourth clock signal 414 is equal to just 1/4 of a one time period of the clock signal.
By synthesizing the first to fourth clock signals 411, 412, 413, and 414, a frequency multiplying circuit can be realized to have a frequency larger 4 times than that of the first clock signal.
However, in the above-mentioned conventional circuit, a method is used in which an external clock signal and a clock signal which has passed through the sequences of delay circuits are compared to correct for a phase difference and a delay difference in order to generate a frequency multiplied clock signal.
For this reason, there is a problem in that a long period of time is necessary until the phase difference is eliminated. Also, there is another problem in that a setup time is long so that power consumption increases in association with the long setup time.